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august 2014 docid025457 rev 2 1 / 13 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. www.st.com STL42P6LLF6 p - channel 60 v, 0.02 typ., 42 a stripfet? f6 power mosfet in a powerflat? 5x6 package datasheet - preliminary data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STL42P6LLF6 60 v 0.028 @ 10 v 42 a ? very low on - resistance ? very low gate charge ? high avalanche ruggedness ? low gate drive power loss applications ? switching applications description this device is an n - channel power mosfet developed using the stripfet? f6 technology with a new trench gate structure. the resulting power mosfet exhibits a very low r ds(on) in all packages. table 1: device summary order code marking package packaging STL42P6LLF6 42p6llf6 powerflat ? 5x6 tape and reel for the p - channel power mosfet, actual polarity of voltages and current have to be reversed. 1 2 3 4 powerfl a t?5x6
contents STL42P6LLF6 2 / 13 docid025457 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 3 test circuits ................................ ................................ ..................... 6 4 package mechanical data ................................ ............................... 7 4.1 powerflat 5x6 type s - r mechanical data and footprint .................. 7 4.2 packaging powerflat? 5x6 tape and reel ................................ ... 10 5 revision history ................................ ................................ ............ 12
STL42P6LLF6 electrical ratings docid025457 rev 2 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 60 v v gs gate - source voltage 20 v i d (1) drain current (continuous) at t c = 25 c 42 a i d (1) drain current (continuous) at t c = 100 c 30 a i d (1) (2) drain current (pulsed) 168 a i d (3) drain current (continuous) at t pcb = 25 c 9 a i d (3) drain current (continuous) at t pcb = 100 c 3.3 a i dm (3) (2) drain current (pulsed) 36 a p tot total dissipation at t c = 25 c 100 w p tot total dissipation at t pcb = 25 c 4.8 w t j t stg operating junction temperature storage temperature - 55 to 175 c notes: (1) the value is according to r thj - case. (2) pulse width is limited by safe operating area. (3) the value is according to r thj - pcb. table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max. 1.5 c/w r thj - pcb (1) thermal resistance junction - pcb max. 31.3 c/w notes: (1) when mounted on fr - 4 board of 15 mm 2 , 2 oz cu, t <10 sec. for the p - channel power mosfet, actual polarity of voltages and current have to be reversed.
electrical characteristics STL42P6LLF6 4 / 13 docid025457 rev 2 2 electrical characteristics (t case = 25 c unless otherwise specified). table 4: on /off states symbol parameter test conditions min. typ. max. un it v (br)dss drain - source breakdown voltage v gs = 0, i d = 250 a 60 v i dss zero gate voltage drain current v gs = 0, v ds = 60 v 1 a v gs = 0, v ds = 60 v, t c =125 c 10 a i gss gate - body leakage current v ds = 0, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 4.5 a 0.02 0.028 v gs = 4.5 v, i d = 4.5 a 0.035 0.045 table 5: dynamic symbol parameter test conditions min. typ. max. uni t c iss input capacitance v ds = 48 v, f = 1 mhz, v gs = 0 - 1720 - pf c oss output capacitance - 220 - pf c rss reverse transfer capacitance - 106 - pf q g total gate charge v dd = 48 v, i d = 9 a, v gs = 4.5 v (see figure 3 ) - 30 - nc q gs gate - source charge - tbd - nc q gd gate - drain charge - tbd - nc table 6: switching times symbol parameter test conditions min. typ. max. uni t t d(on) turn - on delay time v dd = 48 v, i d = 4.5 a, r g = 4.7 , v gs = 10 v (see figure 2 ) - tbd - ns t r rise time - tbd - ns t d(off) turn - off delay time - tbd - ns t f fall time - tbd - ns for the p - channel power mosfet, a ctual polarity of voltages and current have to be reversed.
STL42P6LLF6 electrical characteristics docid025457 rev 2 5 / 13 table 7: source - drain diode symbol parameter test conditions min . typ. ma x. uni t i sd (1) source - drain current - 42 a i sdm source - drain current (pulsed) - 168 a v sd (2) forward on voltage v gs = 0, i sd = 4.5 a - 1.1 v t rr reverse recovery time i sd = 9 a, di/dt = 100 a/s v dd = 16 v, t j = 150 c (see figura 4 ) - tbd ns q rr reverse recovery charge - tbd nc i rrm reverse recovery current - tbd a notes: (1) pulse width limited by safe operating area. (2) pulse duration = 300 s, duty cycle 1.5%. for the p - channel power mosfet, actual polarity of voltages and current have to be reversed.
test circuits STL42P6LLF6 6 / 13 docid025457 rev 2 3 test circuits figure 2 : switching times test circuit for resistive load figure 3 : gate charge test circuit figure 4 : test circuit for inductive load switching and diode recovery times
STL42P6LLF6 package mechanical data docid025457 rev 2 7 / 13 4 package mechanical data in order to meet environmental requireme nts, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 4.1 powerflat 5x6 type s - r mechanical data and footprint figure 5 : powerflat? 5x6 type s - r package outline pin 1 identification pin 1 identification side v iew t op v iew bottom v iew 5 8 4 1 4 1 5 8
package mechanical data STL42P6LLF6 8 / 13 docid025457 rev 2 table 8: powerflat? 5x6 type s - r mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 d2 4.11 4.31 e 5.95 6.15 6.35 e 1.27 e2 3.50 3.70 e3 2.35 2.55 e4 0.40 0.60 e5 0.08 0.28 k 1.275 1.575 l 0.60 0.80
STL42P6LLF6 package mechanical data docid025457 rev 2 9 / 13 figure 6 : recommended footprint all dimensions are in mm.
package mechanical data STL42P6LLF6 10 / 13 docid025457 rev 2 4.2 packaging powerflat? 5x6 tape and reel figure 7 : powerflat? 5x6 tape all dimensions are in millimeters. figure 8 : powerflat? 5x6 package orientation in carrier tape
STL42P6LLF6 package mechanical data docid025457 rev 2 11 / 13 figure 9 : powerflat? 5x6 reel
revision history STL42P6LLF6 12 / 13 docid025457 rev 2 5 revision history table 9: document revision history date revision changes 28 - oct - 2013 1 first release. 25 - aug - 2014 2 modified: figure 1: "internal schematic diagram" updated: section 10: "package mechanical data" minor text changes
STL42P6LLF6 docid025457 rev 2 13 / 13 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics C all rights reserved

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